In one existing approach, a memory cell includes two PMOS transistors coupled with two NMOS transistors that form two cross-coupled pairs. The sources of each PMOS transistor are coupled together and are configured to receive operational voltage VDD for the memory cell. The source and the bulk of each PMOS transistor are physically far apart, but are permanently coupled by a metal line in a strap cell area. As a result, the source and the bulk of each PMOS transistor are electrically coupled together. Because of the physical distance between the source and the bulk, the voltages at the source and at the bulk of the PMOS transistors are often different at power-on. In such a situation, a current exists and flows between the source and the bulk. The magnitude of the current is unpredictable.
Like reference symbols in the various drawings indicate like elements.